Synopsys CEO Sassine Ghazi: AI Models Turn Over Every 3-4 Months, Chip Design Cycles Under Pressure From 18 Months Toward 9, R&D Spending Keeps Rising
In a keynote interview at SEMICON West, Sassine Ghazi, president and CEO of Synopsys, explained the core tension: AI models change every three to four months, while chip design cycles currently take about 18 months and are being compressed by customers. Autonomous agents can now handle spec-to-verified-RTL, but physical implementation and sign-off still depend on human engineers. As customers push for faster delivery, EDA companies' R&D spending continues to increase rather than decrease.
ImportanceMaterialEvidenceE3 inspectableWrite-upStandard
When asked what keeps him up at night, Sassine Ghazi, president and CEO of Synopsys, answered with three words repeated: pace, pace, pace. The interview took place at SEMICON West in October 2026, conducted by Semiconductor Engineering editor-in-chief Ed Sperling before a live audience.
Ghazi's account of where automation actually stands is honest. He confirmed that Synopsys already has customers using autonomous agents to move from a spec to verified RTL — a step that used to require many human engineers working for months. But he was equally clear that physical implementation, physical verification, and chip sign-off are not yet autonomous.
For EDA companies, AI has not cut R&D spending. Customers are pushing design cycles from 18 months down to 14, to a year, and system companies are asking for shorter than nine months. Synopsys must use AI tools to meet that pace, but developing, deploying, and continuously optimizing those AI tools itself requires more investment. Interviewer Ed Sperling noted that EDA has always exceeded almost every other hardware company in R&D as a percentage of revenue; Ghazi confirmed that trend has not changed and that investment is actually continuing to increase, not decrease.