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NewsStructural3 min readDisconfirmAI Editorial

SEMICON West 2026: AI Computing Bottlenecks Expand from Transistor Scaling to System-Level Integration

Patrick Vandenameele, CEO of imec, stated at SEMICON West 2026 that while AI data centers are engineering marvels, they do not represent scaling in the semiconductor sense but rather multiplication. Packaging, photonics, power delivery, and test are converging into a coupled optimization problem, where improving any one aspect may shift the bottleneck elsewhere. This transition means that constraints on computing power expansion are no longer concentrated at a single process node but are distributed across the intersections of multiple engineering disciplines.

2026-10-22 15:05 GMT+8

When Patrick Vandenameele, CEO of imec, spoke about AI data centers at SEMICON West 2026, he posed a question that prompted semiconductor professionals to re-examine their work: These data centers are true engineering marvels, but they do not represent scaling in the semiconductor sense—they look more like multiplication.

This distinction hits at the core constraint of current AI computing growth. Transistor scaling continues, but the bottlenecks facing the industry have expanded: packaging, photonics, power delivery, and test are converging into a coupled optimization problem, where improving any one of them may push the bottleneck elsewhere. More compute increases pressure on memory bandwidth and power delivery; moving memory closer to compute units reduces data movement but concentrates heat; disaggregating large dies into smaller chips can improve yield and allow different functions to use different process nodes, but creates more interfaces that require connection, power, cooling, and test.

Lalitha Immaneni, Vice President of Semiconductor R&D at Intel Foundry, summarized this shift by stating that packaging is no longer just where semiconductor innovation ends, but where system innovation begins. Nitin Deshpande, Vice President of Advanced Packaging at Marvell, was more direct—packaging is becoming a system where compute, memory, interconnects, power, and cooling all converge.

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This system-level coupling has specific implications for manufacturing economics. When certain silicon-HBM combinations are worth up to $30,000, any defect in a single layer of packaging wastes all the value invested in the surrounding components. The Known Good methodology described by Yin Chang, Executive Vice President of ASE, is a response to this: each layer is confirmed qualified before the most expensive components are attached. However, assembly itself creates new uncertainties—the interfaces created by bonding did not exist when individual components were inspected, and heat, pressure, and material interactions can alter the state of the assembly, with some defects only discoverable at the next process step.

For investors in the AI industry, this means that constraints on computing power expansion are no longer concentrated at a single process node or a specific packaging technology, but are distributed across the intersections of multiple engineering fields. Companies capable of solving cross-domain collaborative optimization—whether in design tools, packaging processes, or test infrastructure—will face a competitive landscape that is wider but harder than that of a single technological breakthrough. imec’s judgment of multiplication implies another layer of risk: if the complexity of system integration grows faster than its economic improvement, the expansion of AI infrastructure may face a ceiling defined by cost rather than density.

It should be noted that these judgments come from self-narratives by industry leaders at conferences. The fact that multiple executives pointed to the same issue indicates that the bottleneck is real, but it remains an industry perspective rather than independent measurement. Specific markers to watch in the coming months include: which engineering decisions agentic AI gains autonomous authority over without human approval; whether the pressure on inspection from heterogeneous integration translates into quantifiable yield improvements; and whether co-packaged optics can move from demonstrations to repeatable manufacturing.

Sources

  • semiengineering.com↗
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