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News3 min read·2026-10-21DisconfirmAI Editorial

Samsung at Hot Chips 2026: Why LPDDR5X-PIM Is More Suited to Productization Than HBM-PIM

Samsung Electronics presented its LPDDR5X-PIM approach at Hot Chips 2026. In the Q&A, Samsung denied abandoning HBM-PIM, stating it merely added LPDDR5X-PIM on top. The author infers that Samsung views HBM-PIM as a proof of concept and LPDDR5X-PIM as the productization route, because HBM itself drives up total system power. LPDDR5X-PIM uses 16 banks each paired with a PIM engine, supporting both FP and INT data types, targeting system-level energy efficiency.

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Original publication time 2026-10-21 19:00 GMT+8

The power bottleneck in current AI processors is no longer computation itself. EDN Japan reporter Yusuke Ohara, in his on-site coverage of Hot Chips 2026 (August 23–25, 2026, Stanford University, USA), noted that the majority of AI processor power consumption is dominated by data movement—exchanging data with local or remote memory draws more power than executing the arithmetic operations themselves. Simply boosting compute throughput cannot solve the energy-efficiency problem; reducing data movement is the core challenge.

There are two paths to addressing data-movement power. CIM (Compute-In-Memory, embedding arithmetic units directly within memory cells) is the ultimate approach but comes with many constraints and high engineering difficulty. A more realistic alternative is NMC (Near-Memory Compute): placing arithmetic units beside memory rather than inside it. Samsung's presentation falls under the PIM (Processing-In-Memory) branch of NMC, integrating compute units into LPDDR5X memory chips.

This is not Samsung's first PIM demonstration. At ISSCC 2021, Samsung unveiled HBM-PIM, embedding SIMD engines composed of adders and multipliers into portions of HBM2 banks. The company reported that, compared to pure HBM2 memory mode, performance improved by 2.54× to 2.82× and power consumption dropped by 62%. At the ISSCC 2023 plenary session, AMD CEO Lisa Su showed that installing Samsung HBM-PIM in the Instinct MI100 reduced power consumption by more than 85%. The numbers are impressive, yet Samsung's new route this time is LPDDR5X-PIM rather than continued advancement of HBM-PIM.

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Samsung's stated reason is system-level power. The problem with HBM-PIM is that HBM itself consumes significant power—even if memory-access power drops, the overall power overhead of the HBM stack still drives up total system consumption. In the Q&A, Samsung responded that it is not abandoning HBM-PIM but simply adding LPDDR5X-PIM alongside it. The author infers from this that Samsung treats HBM-PIM as a proof of concept and considers LPDDR5X-PIM the more realistic path toward productization. Structurally, LPDDR5X-PIM divides one DRAM into 16 banks, each paired with a DRAM and PIM unit. The ALU expands from HBM-PIM's FP16-only support to handling both FP and INT; however, according to the author's observation, the operation types appear to have been consolidated from two SIMD engines (ADD and MUL) into MAC only.

The actual PIM workflow proceeds as follows: first, weights and input data are written into memory in normal DRAM mode; then the device switches to PIM mode, the internal engine reads data from DRAM, performs computation, and writes results back; finally, the device returns to DRAM mode and the output is read. This mode-switching process itself takes time, though page 1 of the article does not provide specific switch-latency figures. Samsung also jointly presented a path for building NMC as a CXL device with XCENA, but page 1 does not elaborate on those details.

Sources

  • Source materialedn.itmedia.co.jp↗
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