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NewsMaterial3 min readDisconfirmAI Editorial

Quadric CMO Says RISC-V for AI Acceleration Is a Bad Idea; Breker CEO Argues Control Is the Correct Positioning

In a Semiconductor Engineering roundtable, Quadric's Steve Roddy argues that using RISC-V for AI accelerators fundamentally creates partitioning problems, while Breker CEO Dave Kelf cites real-world cases showing RISC-V's value as an accelerator control processor—custom instructions can reduce partition latency and handle SIMT divergence, but correct instructions do not equal a usable chip, making system-level verification the key bottleneck.

2026-11-12 16:01 GMT+8

Steve Roddy, chief marketing officer at AI chip company Quadric, made a sharp judgment in a Semiconductor Engineering roundtable discussion: using RISC-V for AI acceleration is a "completely bad idea." His argument is not based on RISC-V's inherent lack of capability, but on the cascading consequences of architectural choices—once you create a partition between a programmable processor and an external accelerator, you simultaneously create three problems: data movement, compiler complexity, and interconnect verification.

Roddy's mechanistic reasoning is specific. CPUs excel at pointer chasing and unpredictable thread switching—with 40 threads running, you have no idea what will execute in the next clock cycle. But AI inference does not follow this workload pattern: you know what needs to be done millions of cycles in advance. Therefore, most CPU hardware logic is useless for inference. More critically, while DSPs are closer to what is needed, they are vector machines (vector-by-scalar or vector-by-vector), whereas the most challenging operations in AI are matrix-by-matrix. Thus, his conclusion is that if you start from a CPU to build an accelerator, you are essentially using the wrong starting point to solve a problem that shouldn't exist, then spending billions of dollars to make up for that initial error.

However, Dave Kelf, CEO of verification company Breker, provided counter-evidence from actual projects. He observed that large AI accelerators—whether SIMD or SIMT architectures—are traditionally controlled by complex state machines, which he describes as "hopeless." Four companies he has worked with (both large and small) are replacing state machines with RISC-V processors to drive their accelerators. The reasons are practical: RISC-V allows adding custom instructions for efficient load/store operations to reduce partition latency, and integrating vector or matrix multiplication instructions to handle residual computation when a parallel lane in a SIMT array diverges.

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Kelf cited a specific case: a customer had a SIMT array where occasional divergence occurred in some parallel lanes during massive parallel math operations. When divergence happened, they used the RISC-V control processor to handle the residual computation for that lane, while the rest of the channels continued running on the accelerator. This was not heavy inference on the RISC-V—it was just "enough math processing to keep the whole machine running." He acknowledged this required significant engineering effort, but the results were "quite successful."

The consensus of the roundtable discussion thus became clear: RISC-V’s value in AI systems is not to perform inference calculations itself, but to serve as an orchestration layer—using custom instructions to manage data flow between accelerators, reduce partition latency, and handle edge cases. Roddy also conceded that "you can get value out of tweaking and tuning a processor for the control function," though he did not believe it should be used for heavy inference.

But the discussion revealed a frequently overlooked layer: correct instructions do not guarantee a working chip. Ewald Liess of SignatureIP pointed out that when multiple RISC-V cores coexist with an accelerator in the same system, cache-coherency corner cases and traffic bursts can lead to interconnect deadlocks. An instruction may execute perfectly at the ISA level, but if the required data burst is unavailable, the chip will still fail. Francisca Tan of Siemens EDA added the dimension of observability—tracing custom instructions, system-level performance monitoring, and embedded analytics are indispensable during silicon debugging.

The practical implication for chip architects from this discussion is that RISC-V’s customization capabilities have clear applicability boundaries in the AI context. It is suitable for orchestration, control, and handling edge cases; it is not suitable for being a matrix inference engine. But even within its "suitable" range, between correct instructions and a usable system lie three verification hurdles: cache coherency, interconnect deadlocks, and performance observability.

Sources

  • semiengineering.com↗
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