Monks Investment Trust Quarterly Review: Winners in the AI Supply Chain Depend on Where the Next Bottleneck Is
Monks Investment Trust explains a key distinction in AI infrastructure investment: suppliers addressing the most severe current bottlenecks are not necessarily future winners, because bottlenecks are filled by capital; the truly durable positioning lies in identifying where the next constraint will be—inter-chip connectivity, agent coordination logic, wafer fabrication, and memory deposition.
There is a time-dimension issue that is easily overlooked in AI infrastructure investment. When a specific link becomes the most severe bottleneck, companies that solve it earn excess returns—but these high returns themselves attract capital to fill that bottleneck. Once the bottleneck is resolved, excess profits compress. The real question is not who benefits from current AI demand, but where the next constraint will appear.
In its October 2026 quarterly review, Monks Investment Trust explicitly drew this distinction. It wrote that so far, the biggest winners have been suppliers addressing the most severe bottlenecks, but many chokepoints may be relatively easy to fix, and the exceptional returns they generate may not persist. The fund’s core AI holdings—NVIDIA, Taiwan Semiconductor Manufacturing Company (TSMC), and Amazon—are positioned as durable building blocks of the system, rather than merely beneficiaries of today’s shortage.
Around this core, Monks tilted toward companies solving capacity constraints this quarter. Specifically, it added to positions in four semiconductor equipment companies, including Disco (whose equipment grinds and polishes wafers) and Kokusai (whose machines deposit layers used in memory chips), citing their dominance at critical steps in the manufacturing process. As technology evolves, new constraints are emerging: Astera Labs’ connectivity chips move data between expensive AI chips to ensure they do not sit idle; SoftBank provides undervalued exposure to the logic chips needed for agent coordination through its holding of Arm, a logic chip designer.