AMD Launches Versal TR Chips: Built-in Silicon Backside Physical Attack Protection Simplifies AI Edge Security Design
AMD introduces the first adaptive SoC with integrated silicon backside physical attack protection, aiming to reduce hardware security costs and complexity for AI edge devices.
US semiconductor company AMD announced the Versal™ tamper-resistant (TR) device series on November 12, 2026. This marks the industry's first adaptive SoC or FPGA-based product to integrate direct protection against silicon backside physical attacks, built upon the Versal AI Edge Series Gen 2 platform.
The core technology involves bonding a sensor-based protection die to the main compute die using 3D active-on-active technology, shielding the entire backside of the device. This design detects physical attacks and prevents booting if the protection die is tampered with or removed, while maintaining high-performance heterogeneous processing capabilities.
For sectors such as data center networking, fintech, defense, and critical industrial infrastructure, customers previously had to build custom solutions involving mechanical enclosures, ASICs, and other components to defend against advanced physical attacks. This approach added development costs, specialist resources, and verification efforts. The Versal TR devices integrate heterogeneous computing with enhanced security features into a single chip, reducing the need for separate compute, security, and enclosure-based protection components.
Beyond backside protection, the series expands hardware acceleration for post-quantum cryptography, including support for ML-DSA and SLH-DSA algorithms, and improves the Application Security Unit (ASU) key vault and Memory Element Aging Sensor (MEAS). Kirk Saban, Corporate Vice President of Product, Software and Solutions at AMD Embedded, stated that this initiative helps customers simplify the development of security-critical systems while preserving performance and flexibility.