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NewsMaterial2 min readDisconfirmAI Editorial

AMD Announces Venice-X EPYC CPUs Returning 3D V-Cache to Data Center with 5.3 GHz Boost Clock for HPC Workloads

AMD plans to launch the Venice-X series of server chips in the second half of 2027, bringing 3D V-Cache technology back to the data center after a four-year hiatus. The series maintains 96 cores and 1152MB of L3 cache while achieving a first-ever 5.3GHz boost clock, supporting PCIe 6.0 and 1.6TB/s memory bandwidth to provide a unified solution for High Performance Computing (HPC).

2026-11-12 05:30 GMT+8

U.S. semiconductor company AMD has announced that its "Venice-X" series of EPYC server processors will launch in the second half of 2027. This marks the return of 3D V-Cache stacked cache technology to the data center after a four-year absence. Following the release of Genoa-X in 2023, the previous Turin generation did not feature an X-model with 3D V-Cache, temporarily removing the technology from the lineup.

The core breakthrough of Venice-X lies in unifying high frequency and large capacity cache, two characteristics that were previously difficult to combine. According to Tom's Hardware, Venice-X will feature 96 cores and 1152MB of L3 cache, matching the specifications of the previous-generation EPYC 9684X (Genoa-X), but with a maximum boost clock increased to 5.3GHz. In contrast, earlier X-series chips typically sacrificed frequency to accommodate the massive stacked cache; for example, Milan-X topped out at 3.5GHz, and Genoa-X at 3.7GHz. Venice-X achieves the highest frequency ceiling within the family for the first time, eliminating the need for users to choose between high-frequency chips and large-cache chips.

Beyond the frequency increase, Venice-X introduces PCIe 6.0 interfaces and relies on the SP7 platform to support a 16-channel memory configuration. Through MRDIMM technology, it achieves per-socket memory bandwidth of 1.6TB/s, nearly four times that of the previous generation. These improvements target High Performance Computing (HPC) workloads, particularly functional verification tasks in Electronic Design Automation (EDA).

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Phil Steinke, an AMD Fellow, stated that AMD currently runs EDA workloads by mixing high-frequency CPUs and 3D V-Cache CPUs, as the high-frequency parts historically offered better clock speeds than the cache-heavy parts. Venice-X removes this dichotomy, allowing a single chip to possess both cache advantages and frequency advantages. According to Steinke, for certain logic simulation workloads, 3D V-Cache can improve performance by 40% and double instructions per clock (IPC).

Although the exact number of SKUs, base frequencies, and Thermal Design Power (TDP) have not been fully disclosed, the TDP is expected to be in the range of 400 to 600 watts. The launch of Venice-X signifies AMD's continued strategy of technical differentiation for specialized server loads in the Zen 6 architecture era.

Sources

  • tomshardware.comTom's Hardware↗
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