Synopsys CEO Sassine Ghazi: AI Models Turn Over Every 3-4 Months, Chip Design Cycles Under Pressure From 18 Months Toward 9, R&D Spending Keeps Rising

When asked what keeps him up at night, Sassine Ghazi, president and CEO of Synopsys, answered with three words repeated: pace, pace, pace. The interview took place at SEMICON West in October 2026, conducted by Semiconductor Engineering editor-in-chief Ed Sperling before a live audience.

Ghazi's account of where automation actually stands is honest. He confirmed that Synopsys already has customers using autonomous agents to move from a spec to verified RTL — a step that used to require many human engineers working for months. But he was equally clear that physical implementation, physical verification, and chip sign-off are not yet autonomous.

For EDA companies, AI has not cut R&D spending. Customers are pushing design cycles from 18 months down to 14, to a year, and system companies are asking for shorter than nine months. Synopsys must use AI tools to meet that pace, but developing, deploying, and continuously optimizing those AI tools itself requires more investment. Interviewer Ed Sperling noted that EDA has always exceeded almost every other hardware company in R&D as a percentage of revenue; Ghazi confirmed that trend has not changed and that investment is actually continuing to increase, not decrease.

Here is a structural point worth noting for investors: EDA companies' revenue growth depends on customer design activity volume, which in turn depends on AI model iteration speed. The faster models change, the greater the demand for custom silicon, and the higher EDA revenue — but EDA companies' own margins may face pressure from sustained R&D intensity. Ghazi did not provide specific figures; this inference requires cross-checking against Synopsys financial reports.